1. Field of the Invention
The present invention relates to a gate signal line drive circuit and a display device using the drive circuit. In particularly, the present invention relates to a reduction in power consumption in a gate signal line drive circuit.
2. Description of the Related Art
Up to now, for example, liquid crystal display devices may employ a system in which a shift register circuit disposed in a gate signal line drive circuit that scans gate signal lines is formed on the same substrate as that of thin film transistors (hereinafter referred to as “TFT”) which are arranged in a pixel area of a display screen, that is, a shift register built-in system.
The shift register circuit disposed in the gate signal line drive circuit outputs gate signals Gn which become high voltage in a signal high period which is cyclically repeated, and low voltage in a signal low period which is a period other than the signal high period to corresponding gate signal lines.
FIG. 16 is a circuit diagram illustrating a basic circuit of a shift register circuit in a related art. A transistor T5 is a high voltage application switching element that applies a high voltage to the gate signal lines according to the signal high period. A basic clock signal Vn is input to an input terminal of the transistor T5. The basic clock signal Vn is a clock signal repeated, for example, with four clocks as one cycle, and becomes high voltage in a clock which is a signal high period (period P3) of a gate signal Gn as with a basic clock signal Vn according to the present invention illustrated in FIG. 5.
It is assumed that a voltage to be applied to a gate of the transistor T5 is a node N1, and a voltage to be applied to a gate of a transistor T6 is a node N2. The node N1 and the node N2 become high voltage and low voltage in a period P2 to a period P4, respectively, as with a node N1 and a node N2 according to the present invention illustrated in FIG. 5. In the above period, the transistor T5 becomes in an on state, and outputs a voltage of the basic clock signal Vn to an output terminal OUT connected to the gate signal line. In the period, the transistor T6 is maintained in an off state.